The present invention relates generally to integrated CMOS circuits, and more particularly to a form of such circuits that permits the use of wider operating range power supplies for powering the circuits.
CMOS is the most widely used technology for producing integrated circuits today. Processing techniques have been developed for producing highly dense CMOS integrated circuits. The CMOS integrated circuits have an operating voltage that is the magnitude of the difference between a first and second power supply voltage. The voltages that can be used to power CMOS circuits are dependent upon the physical dimensions of individual devices and the particular processes used. Accordingly, the voltages that are applied to a CMOS device should be limited to below certain voltages that the CMOS device can tolerate. In particular, a voltage applied across the source and drain terminals should not exceed a voltage (VDS) at which a channel breakdown will occur. Likewise, a voltage applied across the gate of a CMOS device should not exceed a voltage (VGS) at which a breakdown of the gate oxide dielectric will occur.
The present invention is directed towards an apparatus and method for allowing circuits to operate over a wider operating voltage range for a given process. Cascoded transistors can be used to allow circuits to operate at higher operating voltages than the voltages at which individual transistors (formed by a given process) can function. However, common techniques for cascoding transistors result in circuits being unable to operate at lower operating voltages. The present invention dynamically biases cascoded transistors in response to the level of the operating voltage, which can vary. Providing separate dynamic bias voltages for N-type and P-type CMOS devices allows circuits using this technique to achieve a wider operating voltage. The wider operating range makes circuits using this technique readily adaptable to a range of power supplies (e.g., different battery configurations) and applications (e.g., driving displays).
According to one aspect of the invention, a dynamic biasing comprises a comparator, a first biasing circuit, and a second biasing circuit. The comparator is configured to provide a comparison signal that is in a first state when the operating voltage is greater than the trip point voltage (Vtrip) and that is in a second state when the operating voltage is less than the trip point voltage. The trip point voltage is approximately set to be 500 mV less than the maximum operating voltage the process allows. The first biasing circuit provides the bias voltage for all the cascoded NMOS transistors. The first bias voltage is proportional to the operating voltage when the comparison signal is in the first state when the operating voltage is less than the trip point, and the bias voltage is fixed at the trip point voltage Vtrip when the comparison signal is in the second state when the operating voltage is higher than the trip point. The second biasing circuit provides the bias voltage for all the cascoded PMOS transistors. The second bias voltage is at a fixed voltage reference such as ground (xe2x80x9cgroundxe2x80x9d) when the comparison signal is in the first state, VDDA less than Vtrip, and is proportional to the magnitude of the difference between the operating voltage and the trip point voltage when the comparison signal is in the second state, VDDA less than Vtrip